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stm32 /stm32wl /STM32WL5x_CM0P /TIM1 /OR1

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Interpret as OR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TIM1_ETR_ADC1_RMP 0 (TI1_RMP)TI1_RMP

Description

option register 1

Fields

TIM1_ETR_ADC1_RMP

TIM1_ETR_ADC1 remapping capability
TI1_RMP

Input Capture 1 remap

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32