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stm32 /stm32wl /STM32WL5x_CM0P /TIM17 /CR2

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Interpret as CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CCPC)CCPC 0 (CCUS)CCUS 0 (CCDS)CCDS 0 (OIS1)OIS1 0 (OIS1N)OIS1N

Description

TIM16/TIM17 control register 2

Fields

CCPC

CCPC
CCUS

CCUS
CCDS

CCDS
OIS1

OIS1
OIS1N

OIS1N

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32