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stm32 /stm32wl /STM32WL5x_CM0P /TZIC /MISR1

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Interpret as MISR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TZICMF)TZICMF 0 (TZSCMF)TZSCMF 0 (AESMF)AESMF 0 (RNGMF)RNGMF 0 (SUBGHZSPIMF)SUBGHZSPIMF 0 (PWRMF)PWRMF 0 (FLASHIFMF)FLASHIFMF 0 (DMA1MF)DMA1MF 0 (DMA2MF)DMA2MF 0 (DMAMUX1MF)DMAMUX1MF 0 (FLASHMF)FLASHMF 0 (SRAM1MF)SRAM1MF 0 (SRAM2MF)SRAM2MF 0 (PKAMF)PKAMF

Description

TZIC status register 1

Fields

TZICMF

TZICMF
TZSCMF

TZSCMF
AESMF

AESMF
RNGMF

RNGMF
SUBGHZSPIMF

SUBGHZSPIMF
PWRMF

PWRMF
FLASHIFMF

FLASHIFMF
DMA1MF

DMA1MF
DMA2MF

DMA2MF
DMAMUX1MF

DMAMUX1MF
FLASHMF

FLASHMF
SRAM1MF

SRAM1MF
SRAM2MF

SRAM2MF
PKAMF

PKAMF

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32