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stm32 /stm32wl /STM32WL5x_CM4 /DBGMCU /APB1FZR1

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Interpret as APB1FZR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_TIM2_STOP)DBG_TIM2_STOP 0 (DBG_RTC_STOP)DBG_RTC_STOP 0 (DBG_WWDG_STOP)DBG_WWDG_STOP 0 (DBG_IWDG_STOP)DBG_IWDG_STOP 0 (DBG_I2C1_STOP)DBG_I2C1_STOP 0 (DBG_I2C2_STOP)DBG_I2C2_STOP 0 (DBG_I2C3_STOP)DBG_I2C3_STOP 0 (DBG_LPTIM1_STOP)DBG_LPTIM1_STOP

Description

DBGMCU CPU1 APB1 Peripheral Freeze Register 1

Fields

DBG_TIM2_STOP

TIM2 stop in CPU1 debug
DBG_RTC_STOP

RTC stop in CPU1 debug
DBG_WWDG_STOP

WWDG stop in CPU1 debug
DBG_IWDG_STOP

IWDG stop in CPU1 debug
DBG_I2C1_STOP

I2C1 SMBUS timeout stop in CPU1 debug
DBG_I2C2_STOP

I2C2 SMBUS timeout stop in CPU1 debug
DBG_I2C3_STOP

I2C3 SMBUS timeout stop in CPU1 debug
DBG_LPTIM1_STOP

LPTIM1 stop in CPU1 debug

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32