stm32 /stm32wl /STM32WL5x_CM4 /DBGMCU /C2APB1FZR1

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Interpret as C2APB1FZR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_TIM2_STOP)DBG_TIM2_STOP 0 (DBG_RTC_STOP)DBG_RTC_STOP 0 (DBG_IWDG_STOP)DBG_IWDG_STOP 0 (DBG_I2C1_STOP)DBG_I2C1_STOP 0 (DBG_I2C2_STOP)DBG_I2C2_STOP 0 (DBG_I2C3_STOP)DBG_I2C3_STOP 0 (DBG_LPTIM1_STOP)DBG_LPTIM1_STOP

Description

DBGMCU CPU2 APB1 Peripheral Freeze Register 1 [dual core device

Fields

DBG_TIM2_STOP

DBG_TIM2_STOP

DBG_RTC_STOP

DBG_RTC_STOP

DBG_IWDG_STOP

DBG_IWDG_STOP

DBG_I2C1_STOP

DBG_I2C1_STOP

DBG_I2C2_STOP

DBG_I2C2_STOP

DBG_I2C3_STOP

DBG_I2C3_STOP

DBG_LPTIM1_STOP

DBG_LPTIM1_STOP

Links

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