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stm32 /stm32wl /STM32WL5x_CM4 /IPCC /IC1TOC2SR

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Interpret as IC1TOC2SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH1F)CH1F 0 (CH2F)CH2F 0 (CH3F)CH3F 0 (CH4F)CH4F 0 (CH5F)CH5F 0 (CH6F)CH6F

Description

IPCC processor 1 to processor 2 status register

Fields

CH1F

CH1F
CH2F

CH2F
CH3F

CH3F
CH4F

CH4F
CH5F

CH5F
CH6F

CH6F

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32