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stm32 /stm32wl /STM32WL5x_CM4 /RCC /APB1RSTR2

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Interpret as APB1RSTR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPUART1RST)LPUART1RST 0 (LPTIM2RST)LPTIM2RST 0 (LPTIM3RST)LPTIM3RST

Description

APB1 peripheral reset register 2

Fields

LPUART1RST

Low-power UART 1 reset
LPTIM2RST

Low-power timer 2 reset
LPTIM3RST

Low-power timer 3 reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32