stm32 /stm32wl /STM32WL5x_CM4 /RCC /C2AHB1ENR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as C2AHB1ENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA1EN)DMA1EN 0 (DMA2EN)DMA2EN 0 (DMAMUX1EN)DMAMUX1EN 0 (CRCEN)CRCEN

Description

CPU2 AHB1 peripheral clock enable register

Fields

DMA1EN

CPU2 DMA1 clock enable

DMA2EN

CPU2 DMA2 clock enable

DMAMUX1EN

CPU2 DMAMUX1 clock enable

CRCEN

CPU2 CRC clock enable

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