stm32 /stm32wl /STM32WL5x_CM4 /RCC /C2AHB2SMENR

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Interpret as C2AHB2SMENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GPIOASMEN)GPIOASMEN 0 (GPIOBSMEN)GPIOBSMEN 0 (GPIOCSMEN)GPIOCSMEN 0 (GPIOHSMEN)GPIOHSMEN

Description

CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]

Fields

GPIOASMEN

IO port A clock enable during CPU2 CSleep mode.

GPIOBSMEN

IO port B clock enable during CPU2 CSleep mode.

GPIOCSMEN

IO port C clock enable during CPU2 CSleep mode.

GPIOHSMEN

IO port H clock enable during CPU2 CSleep mode.

Links

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