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Description
CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]
Fields
| LPUART1SMEN | Low power UART 1 clock enable during CPU2 CSleep and CStop mode
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| LPTIM2SMEN | Low power timer 2 clocks enable during CPU2 CSleep and CStop modes.
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| LPTIM3SMEN | Low power timer 3 clocks enable during CPU2 CSleep and CStop modes.
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