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stm32 /stm32wl /STM32WL5x_CM4 /RCC /C2APB2ENR

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Interpret as C2APB2ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADCEN)ADCEN 0 (TIM1EN)TIM1EN 0 (SPI1EN)SPI1EN 0 (USART1EN)USART1EN 0 (TIM16EN)TIM16EN 0 (TIM17EN)TIM17EN

Description

CPU2 APB2 peripheral clock enable register [dual core device only]

Fields

ADCEN

ADC clocks enable
TIM1EN

CPU2 TIM1 timer clock enable
SPI1EN

CPU2 SPI1 clock enable
USART1EN

CPU2 USART1clocks enable
TIM16EN

CPU2 TIM16 timer clock enable
TIM17EN

CPU2 TIM17 timer clock enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32