stm32 /stm32wl /STM32WL5x_CM4 /RCC /C2APB3ENR

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Interpret as C2APB3ENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SUBGHZSPIEN)SUBGHZSPIEN

Description

CPU2 APB3 peripheral clock enable register [dual core device only]

Fields

SUBGHZSPIEN

CPU2 sub-GHz radio SPI clock enable

Links

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