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stm32 /stm32wl /STM32WL5x_CM4 /SYSCFG /IMR1

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Interpret as IMR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RTCSTAMPTAMPLSECSSIM)RTCSTAMPTAMPLSECSSIM 0 (RTCSSRUIM)RTCSSRUIM 0 (EXTI5IM)EXTI5IM 0 (EXTI6IM)EXTI6IM 0 (EXTI7IM)EXTI7IM 0 (EXTI8IM)EXTI8IM 0 (EXTI9IM)EXTI9IM 0 (EXTI10IM)EXTI10IM 0 (EXTI11IM)EXTI11IM 0 (EXTI12IM)EXTI12IM 0 (EXTI13IM)EXTI13IM 0 (EXTI14IM)EXTI14IM 0 (EXTI15IM)EXTI15IM

Description

SYSCFG CPU1 interrupt mask register 1

Fields

RTCSTAMPTAMPLSECSSIM

RTCSTAMPTAMPLSECSSIM
RTCSSRUIM

RTCSSRUIM
EXTI5IM

EXTI5IM
EXTI6IM

EXTI6IM
EXTI7IM

EXTI7IM
EXTI8IM

EXTI8IM
EXTI9IM

EXTI9IM
EXTI10IM

EXTI10IM
EXTI11IM

EXTI11IM
EXTI12IM

EXTI12IM
EXTI13IM

EXTI13IM
EXTI14IM

EXTI14IM
EXTI15IM

EXTI15IM

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32