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stm32 /stm32wl /STM32WL5x_CM4 /TIM2 /TIM2_TISEL

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Interpret as TIM2_TISEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TI1SEL0TI2SEL

Description

TIM2 timer input selection register

Fields

TI1SEL

TI1SEL
TI2SEL

TI2SEL

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32