Regviz

stm32 /stm32wl /STM32WLE5_CM4 /DBGMCU /APB1FZR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as APB1FZR2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wl/STM32WLE5_CM4/DBGMCU/APB1FZR2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_LPTIM2_STOP)DBG_LPTIM2_STOP 0 (DBG_LPTIM3_STOP)DBG_LPTIM3_STOP

Description

DBGMCU CPU1 APB1 Peripheral Freeze Register 2

Fields

DBG_LPTIM2_STOP

DBG_LPTIM2_STOP
DBG_LPTIM3_STOP

DBG_LPTIM3_STOP

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32