DTB_CONF register
| ADC_DBG_CONF | ADC_DBG_CONF[3:0]: use for debug purpose. |
| ADC_DTB_CONF | ADC_DTB_CONF[1:0]: configure the DTB output. 00: DTB bus is all 0 01: output the ADC_BUSY, ADC_EOC, offset compensation data[11:0] on the ADC_DTB 10: output the DS information on the ADC_DTB 11: select states of the FSM and enable ADC serial output Note: detailed DTB configurations are available in the Table 38 in IUM |
| DTB_SER_SEL | DTB_SER_SEL: DTB serial output selection when ADC_DB_CONF[1:0]=3d 0: pre down-sampler with offset compensation data 1: post down-sampler data |
| FSM_STATE | FSM_STATE[7:0]: show the state of the state machine. Bit 0: IDLE Bit 1: Reserved Bit 2: ADC setup phase Bit 3: Reserved Bit 4: ADC_START_CONV resynchronization Bit 5: Reserved Bit 6: ADC mode Bit 7: sequence mode |
| FSM_CUR_STATE | FSM_CUR_STATE[2:0]: show the last executed state by the state machine. 000: IDLE mode 001: Reserved 010: ADC setup phase 011: Reserved 100: ADC_START_CONV resynchronization 101: Reserved 110: ADC mode 111: sequence mode |