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stm32 /stm32wl3 /STM32WL33 /DAC /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMAUDR)DMAUDR

Description

SR register

Fields

DMAUDR

DMAUDR: DAC channel DMA underrun flag This bit is set by hardware and cleared by

software (by writing it to 1).

0: No DMA underrun error condition occurred for DAC channel

1: DMA underrun error condition occurred for DAC channel (the currently selected trigger is

driving DAC channel conversion at a frequency higher than the DMA service capability rate)

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32