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stm32 /stm32wl3 /STM32WL33 /DBGMCU /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_SLEEP)DBG_SLEEP 0 (DBG_STOP)DBG_STOP

Description

CR register

Fields

DBG_SLEEP

Allow debug of the CPU in SLEEP mode

  • 0: Normal operation. All clocks will be disabled automatically in SLEEP mode
  • 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during SLEEP mode, allowing full CPU debug capability. On exit from SLEEP mode, the clock settings will be set to the SLEEP mode exit state.
DBG_STOP

Allow debug of the CPU in DEEPSTOP mode

  • 0: Normal operation. All clocks will be disabled automatically in STOP mode
  • 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during STOP mode, allowing full CPU debug capability. On exit from STOP mode, the clock settings will be set to the STOP mode exit state.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32