Regviz

stm32 /stm32wl3 /STM32WL33 /DBGMCU /DBG_APB0_FZ

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DBG_APB0_FZ

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wl3/STM32WL33/DBGMCU/DBG_APB0_FZ#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_TIM2_STOP)DBG_TIM2_STOP 0 (DBG_TIM16_STOP)DBG_TIM16_STOP 0 (DBG_RTC_STOP)DBG_RTC_STOP 0 (DBG_IWDG_STOP)DBG_IWDG_STOP

Description

DBG_APB0_FZ register

Fields

DBG_TIM2_STOP

TIM2 stop in the CPU debug

  • 0: Normal operation. TIM2 continues to operate while the CPU is in debug mode
  • 1: Stop in debug. TIM2 is frozen while the CPU is in debug mode.
DBG_TIM16_STOP

TIM16 stop in the CPU debug

  • 0: Normal operation. TIM16 continues to operate while the CPU is in debug mode
  • 1: Stop in debug. TIM16 is frozen while the CPU is in debug mode.
DBG_RTC_STOP

RTC stop in CPU debug

  • 0: Normal operation. RTC continues to operate while the CPU is in debug mode
  • 1: Stop in debug. RTC is frozen while the CPU is in debug mode.
DBG_IWDG_STOP

IWDG stop in the CPU debug

  • 0: Normal operation. IWDG continues to operate while the CPU is in debug mode
  • 1: Stop in debug. IWDG is frozen while the CPU is in debug mode.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32