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stm32 /stm32wl3 /STM32WL33 /DBGMCU /DBG_APB1_FZ

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Interpret as DBG_APB1_FZ

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_I2C1_STOP)DBG_I2C1_STOP 0 (DBG_I2C2_STOP)DBG_I2C2_STOP

Description

DBG_APB1_FZ register

Fields

DBG_I2C1_STOP

I2C1 SMBUS timeout stop in CPU debug

  • 0: Normal operation. I2C1 SMBUS timeout continues to operate while the CPU is in debug mode
  • 1: Stop in debug. I2C1 SMBUS timeou is frozen while the CPU is in debug mode.
DBG_I2C2_STOP

I2C2 SMBUS timeout stop in CPU debug

  • 0: Normal operation. I2C2 SMBUS timeout continues to operate while the CPU is in debug mode
  • 1: Stop in debug. I2C2 SMBUS timeou is frozen while the CPU is in debug mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32