DMA_CCRx register
| EN | EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled |
| TCIE | TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled |
| HTIE | HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled |
| TEIE | TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled |
| DIR | DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral. 1: Read from memory |
| CIRC | CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled |
| PINC | PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled |
| MINC | MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled |
| PSIZE | PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits |
| MSIZE | MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits |
| PL | PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high |
| MEM2MEM | MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled |