stm32 /stm32wl3 /STM32WL33 /DMA /DMA_CNDTR4

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Interpret as DMA_CNDTR4

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0NDT

Description

DMA_CNDTRx register

Fields

NDT

NDT[15:0]: Number of data to transfer

Number of data to be transferred (0 up to 65535). This register can only be written when the

channel is disabled. Once the channel is enabled, this register is read-only, indicating the

remaining bytes to be transmitted. This register decrements after each DMA transfer.

Once the transfer is completed, this register can either stay at zero or be reloaded

automatically by the value previously programmed if the channel is configured in auto-reload

mode.

If this register is zero, no transaction can be served whether the channel is enabled or not.

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