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stm32 /stm32wl3 /STM32WL33 /LPAWUR /FRAME_CONFIG0

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Interpret as FRAME_CONFIG0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PREAMBLE_THRESHOLD_COUNT 0 (SYNC_LENGTH)SYNC_LENGTH 0SYNC_THRESHOLD_COUNT 0PAYLOAD_LENGTH 0SLOW_CLK_CYCLE_PER_BIT_CNT

Description

FRAME_CONFIG0 register

Fields

PREAMBLE_THRESHOLD_COUNT

The number of transitions for preamble detection when receiving the manchester encoded preamble.
SYNC_LENGTH

Frame sync pattern length ( Manchester encoded ).
SYNC_THRESHOLD_COUNT

detection threshold when receivng the Frame sync ( Manchester encoded).
PAYLOAD_LENGTH

The number of data Bytes in the payload ( decoded ).
SLOW_CLK_CYCLE_PER_BIT_CNT

The number of expected slow clock cycle per each manchester coded bit.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32