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stm32 /stm32wl3 /STM32WL33 /LPAWUR /FRAME_CONFIG1

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Interpret as FRAME_CONFIG1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0KI0KP0FRAME_SYNC_COUNTER_TIMEOUT 0 (PREAMBLE_ENABLE)PREAMBLE_ENABLE 0 (TREC_LOOP_ALGO_SEL)TREC_LOOP_ALGO_SEL

Description

FRAME_CONFIG1 register

Fields

KI

ki gain value for the timing recovery loop.
KP

kp gain value for the timing recovery loop.
FRAME_SYNC_COUNTER_TIMEOUT

The timeout in manchester encoded bits for the Frame Sync,it represents the number of samples after which in case the frame sync is not detected a sync_error is raised.
PREAMBLE_ENABLE

Preamble detection enable
TREC_LOOP_ALGO_SEL

Timing recovery loop algorithm selection:

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32