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stm32 /stm32wl3 /STM32WL33 /LPAWUR /RF_CONFIG

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Interpret as RF_CONFIG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ED_SWITCH)ED_SWITCH 0CLKDIV0AGC_LOW_LVL 0 (ED_DC_CTRL)ED_DC_CTRL 0AGC_HIGH_LVL 0ED_ICAL 0 (LPF3_CAL)LPF3_CAL

Description

RF_CONFIG register

Fields

ED_SWITCH
  • 0 : Normal operation (default)
CLKDIV

Calibrate 4kHz clock (programmable divider)
AGC_LOW_LVL

AGC level (Low) (default value: 0x2)
ED_DC_CTRL

DC current subtraction enabling signal (default value: 0x1)
AGC_HIGH_LVL

AGC level (High) (default value: 0x4)
ED_ICAL

Current versus VBAT calibration for ED
LPF3_CAL

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32