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stm32 /stm32wl3 /STM32WL33 /MR_SUBG /AGC0_CTRL

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Interpret as AGC0_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0AGC_HOLD_TIME 0 (AGC_START_ONHOLD)AGC_START_ONHOLD 0 (AGC_EN)AGC_EN

Description

AGC0_CTRL register

Fields

AGC_HOLD_TIME

AGC hold time.
AGC_START_ONHOLD

Start the AGC with a hold phase.
AGC_EN

Enable the AGC

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32