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stm32 /stm32wl3 /STM32WL33 /MR_SUBG /CLKREC_CTRL1

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Interpret as CLKREC_CTRL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKREC_I_GAIN_SLOW 0CLKREC_P_GAIN_SLOW 0 (CLKREC_ALGO_SEL)CLKREC_ALGO_SEL

Description

CLKREC_CTRL1 register

Fields

CLKREC_I_GAIN_SLOW

Integral slow gain for the clock recovery loop (PLL mode only)
CLKREC_P_GAIN_SLOW

Clock recovery slow loop gain (log2)
CLKREC_ALGO_SEL

Symbol timing recovery algorithm selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32