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stm32 /stm32wl3 /STM32WL33 /MR_SUBG /RF_FSM1_TIMEOUT

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Interpret as RF_FSM1_TIMEOUT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SYNTH_SETUP_TIMER

Description

RF_FSM1_TIMEOUT register

Fields

SYNTH_SETUP_TIMER

Timeout management for the RF regulator to stabilize after RF PLL power on

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32