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stm32 /stm32wl3 /STM32WL33 /MR_SUBG /SYNTH2_ANA_ENG

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Interpret as SYNTH2_ANA_ENG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RFD_PLL_VCO_ALC_AMP 0 (RFD_PLL_LD_WIN_ACC)RFD_PLL_LD_WIN_ACC

Description

SYNTH2_ANA_ENG register

Fields

RFD_PLL_VCO_ALC_AMP

Select the level of max VCO amplitude in amplitude level control loop.
RFD_PLL_LD_WIN_ACC

Select the PLL lock detector window selection:

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32