stm32 /stm32wl3 /STM32WL33 /PWRC /CR1

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Interpret as CR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPMS)LPMS 0 (ENSDNBOR)ENSDNBOR 0 (IBIAS_RUN_AUTO)IBIAS_RUN_AUTO 0 (IBIAS_RUN_STATE)IBIAS_RUN_STATE 0 (APC)APC 0 (ENBORH)ENBORH 0SELBORH 0 (ENBORL)ENBORL

Description

CR1 register

Fields

LPMS

LPMS Low Power Mode Selection Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep.

  • 0: Deep Stop mode (default)
  • 1: Shutdown mode
ENSDNBOR

ENSDNBOR: Enable BOR supply monitoring during shutdown mode.

  • 1: the PD_ALL_SHUTDOWN signal is not set during SHUTDOWN mode
  • 0: the PD_ALL_SHUTDOWN signal is set during SHUTDOWN mode.
IBIAS_RUN_AUTO

IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode.

  • 0: IBIAS control is manual (and controlled by IBIAS_RUN_STATE register)
  • 1: IBIAS control is automatic (default).
IBIAS_RUN_STATE

IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is disabled.

  • 0: IBIAS control is disabled (default).
  • 1: IBIAS control is enabled.
APC

APC Apply Pull-up and pull-down configuration from CPU

  • 1: the I/O pull-up and pull-down configurations defined in the PUCRx and PDCRx registers is applied.
  • 0: the PUCRx and PDCRx are not used to control the I/O pull-up and pull-down configuration of the product I/Os.
ENBORH

ENBORH: enable BORH configuration

  • 1: BORH is enabled, threshold level depends on SELBOR[1:0]
  • 0: BORH off (VBOR0): threshold level for above 1.60V voltage operation.
SELBORH

SELBORH[1:0]: BORH selection of Vbor threshold

  • 11: BORH Level 4(VBOR4): threshold level for above 2.81 V voltage operation.
  • 10: BORH Level 3 (VBOR3): threshold level for above 2.52 V voltage operation
  • 01: BORH Level 2 (VBOR2): threshold level for above 2.21 V voltage operation
  • 00: BORH Level 1 (VBOR1): threshold level for above 2.0V voltage operation.
ENBORL

ENBORL: Enable BORL reset supervising during RUN mode.

  • 0: No BORL is monitored during RUN mode.
  • 1: BORL is monitored during RUN mode (a POR reset will happen if VDDIO goes below 1.6V during RUN mode) (default). Note: Enabling this feature prevents blocking the device if VDDIO goes below supported voltages during RUN.

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