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stm32 /stm32wl3 /STM32WL33 /PWRC /DBGR

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Interpret as DBGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DEEPSTOP2)DEEPSTOP2 0 (SMPSFRDY)SMPSFRDY 0KELVIN_TEST 0DIS_PRECH

Description

DBGR register

Fields

DEEPSTOP2

DEEPSTOP2 low power saving mode emulation enable this bit enable an emulated debug DEEPSTOP low power mode. If emulation is enabled, entering in DEEPSTOP mode, the v12i power domain still enters power saving mode, but its clock and power are maintained.
SMPSFRDY

SMPSFB Force ready check When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR.

  • 0 : no effect (by default)
  • 1 : SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1)
KELVIN_TEST

KELVIN_TEST[2:0]: Enable TEST mode Kelvin for LDO_RF (Write protected by IFR3 key)

  • 000: 0mA (open) (default 0x0)
  • 001 for 1mA
  • 010 for 3mA
  • 011 for 5mA
  • 100 for 8mA
  • 101 for 10mA else: 0mA (open) for other combinations.
DIS_PRECH

DIS_PRECH[2:0]: disable precharge during deepstop (debug) allowed combination are:

  • 111: precharge and SMPS monitoring are disabled (whatever CR5.SMPSLPOPEN)
  • 101: precharge are activated only at deepstop exit (to be used only with CR5.SMPSLPOPEN=1) else: No effect (default 0x0)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32