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stm32 /stm32wl3 /STM32WL33 /PWRC /DBG_STATUS_REG2

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Interpret as DBG_STATUS_REG2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PMU_FSM_STATE 0RAM_FSM_STATE

Description

DBG_STATUS_REG2 register

Fields

PMU_FSM_STATE

PMU_FSM_STATE[3:0]: Indicates the current state of the PMU FSM inside the PWRC.

  • 0000: POR
  • 0001: RUN
  • 0010: DS ENTRY
  • 0011: WAIT1
  • 0100: WAIT2
  • 0101: WAIT
  • 0110: WAIT3
  • 0111: WAIT4
  • 1000: ISOLATION
  • 1001: DEEPSTOP
  • 1010: SHUTDOWN
  • 1011: DEEPSTOP EXIT
RAM_FSM_STATE

RAM_FSM_STATE[1:0]: Indicates the current state of the RAM FSM inside the PWRC:

  • 00: POR
  • 01: POWER UP
  • 10: READY
  • 11: OFF

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32