EXTSRR

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Interpret as EXTSRR

EXTSRR register

DEEPSTOPF	DEEPSTOPF System DeepStop Flag This bit is set by hardware and cleared only by a POR reset or by writing ‘1’ in this bit field 0: System has not been in DEEPSTOP mode 1: System has been in DEEPSTOP mode
RFPHASEF	RFPHASEF RFPHASE Flag This bit is set by hardware after a S3LP wake-up event (S3LP activation); it is cleared either by software, writing ‘1’ in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP. 0: RF IP does not require attention 1: RF IP awake and requesting system attention

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