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stm32 /stm32wl3 /STM32WL33 /PWRC /SR2

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Interpret as SR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SMPSBYPR)SMPSBYPR 0 (SMPSENR)SMPSENR 0 (SMPSRDY)SMPSRDY 0IOBOOTVAL2 0 (REGLPS)REGLPS 0 (REGMS)REGMS 0 (PVDO)PVDO 0IOBOOTVAL

Description

SR2 register

Fields

SMPSBYPR

SMPSBYPR: SMPS Force Bypass Control Replica This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state.
SMPSENR

SMPSENR: SMPS Enable Control Replica This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state.
SMPSRDY

SMPSRDY: SMPS Ready Status This bit provides the information whether SMPS is ready.

  • 0: SMPS regulator is not ready
  • 1: SMPS regulator is ready.
IOBOOTVAL2

Bit3: PB15 input value on VDD33 latched at POR Bit2: PB14 input value on VDD33 latched at POR Bit1: PB13 input value on VDD33 latched at POR Bit0: PB12 input value on VDD33 latched at POR
REGLPS

REGLPS: Regulator Low Power Started This bit provides the information whether low power regulator is ready.

  • 0: LP regulator is not ready.
  • 1: LP regulator is ready.
REGMS

REGMS: Main regulator ready status.

  • 0: The Main regulator is not ready.
  • 1: The Main regulator is ready.
PVDO

PVDO: Power Voltage Detector Output When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is lower than the selected PVD threshold (CR2.PVDLS)
IOBOOTVAL

Bit3: PA11 input value on VDD33 latched at POR Bit2: PA10 input value on VDD33 latched at POR Bit1: PA9 input value on VDD33 latched at POR Bit0: PA8 input value on VDD33 latched at POR

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32