Regviz

stm32 /stm32wl3 /STM32WL33 /RCC /AHBENR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as AHBENR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wl3/STM32WL33/RCC/AHBENR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMAEN)DMAEN 0 (GPIOAEN)GPIOAEN 0 (GPIOBEN)GPIOBEN 0 (CRCEN)CRCEN 0 (RNGEN)RNGEN 0 (AESEN)AESEN

Description

AHBENR register

Fields

DMAEN

DMA and DMAMUX enable Set and enable by software. 0: does not enable 1: enable
GPIOAEN

GPIOA enable. It must be enabled by default
GPIOBEN

GPIOB enable. It must be enabled by default
CRCEN

CRC enable Set and enable by software. 0: does not enable 1: enable
RNGEN

RNG clock enable Set and enable by software. 0: does not enable 1: enable
AESEN

AESEN: AES clock enable. 0: AES IP is clock gated. 1: AES IP is clocked.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32