| DMASMEN | DMA clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: DMA clock disabled in Sleep mode
- 1: DMA clock enabled in Sleep mode (if enabled in DMAEN)
|
| FLASHSMEN | Flash clocks enable during Flash Sleep PD and CPU Sleep mode bit
This bit is set and reset by software.
- 0: Flash clocks are disabled in Flash Sleep PD* and CPU Sleep mode
- 1: Flash clocks are enabled in Sleep mode
Note: Flash Sleep PD is enabled through nvm_control register CONFIG.SLEEP_PD
|
| GPIOASMEN | GPIOA clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: GPIOA clock disabled in Sleep mode
- 1: GPIOA clock enabled in Sleep mode (if enabled by GPIOAEN)
|
| GPIOBSMEN | GPIOB clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: GPIOB clock disabled in Sleep mode
- 1: GPIOB clock enabled in Sleep mode (if enabled in GPIOBEN)
|
| SRAM0SMEN | SRAM0 clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: SRAM0 clock disabled in Sleep mode
- 1: SRAM0 clock enabled in Sleep mode
|
| SRAM1SMEN | SRAM1 clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: SRAM1 clock disabled in Sleep mode
- 1: SRAM1 clock enabled in Sleep mode
|
| CRCSMEN | CRC clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: CRC clock disabled in Sleep mode
- 1: CRC clock enabled in Sleep mode (if enabled in CRCEN)
|
| RNGSMEN | RNG bus clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: RNG bus clock disabled in Sleep mode
- 1: RNG bus clock enabled in Sleep mode (if enabled in RNGEN)
|
| AESSMEN | AES bus clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: AES bus clock disabled in Sleep mode
- 1: AES bus clock enabled in Sleep mode (if enabled in AESEN)
|