| TIM2SMEN | TIM2 bus clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: TIM2 bus clock disabled in Sleep mode
- 1: TIM2 bus clock enabled in Sleep mode (if enabled in TIM2EN)
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| TIM16SMEN | TIM16 bus clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: TIM16 bus clock disabled in Sleep mode
- 1: TIM16 bus clock enabled in Sleep mode (if enabled in TIM16EN)
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| SYSCFGSMEN | SYSCFG bus clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: SYSCFG bus clock disabled in Sleep mode
- 1: SYSCFG bus clock enabled in Sleep mode (if enabled in SYSCFGEN)
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| LCDCSMEN | LCDC bus clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: LCDC bus clock disabled in Sleep mode
- 1: LCDC bus clock enabled in Sleep mode (if enabled in LCDCEN)
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| COMPSMEN | COMP bus clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: COMP bus clock disabled in Sleep mode
- 1: COMP bus clock enabled in Sleep mode (if enabled in COMPEN)
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| DACSMEN | DAC bus clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: DAC bus clock disabled in Sleep mode
- 1: DAC bus clock enabled in Sleep mode (if enabled in DACEN)
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| RTCSMEN | RTC bus clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: RTC bus clock disabled in Sleep mode
- 1: RTC bus clock enabled in Sleep mode (if enabled in RTCEN)
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| LCSCSMEN | LCSC bus clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: LCSC bus clock disabled in Sleep mode
- 1: LCSC bus clock enabled in Sleep mode (if enabled in LCSCEN)
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| WDGSMEN | WDG clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: WDG clock disabled in Sleep mode
- 1: WDG clock enabled in Sleep mode (if enabled in WDGEN)
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| DBGMCUSMEN | DBGMCU clock enable during Sleep mode bit
This bit is set and reset by software.
- 0: DBGMCU clock disabled in Sleep mode
- 1: DBGMCU clock enabled in Sleep mode (if enabled in DBGMCUEN)
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