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stm32 /stm32wl3 /STM32WL33 /RCC /APB1RSTR

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Interpret as APB1RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI1RST)SPI1RST 0 (ADCRST)ADCRST 0 (LPUARTRST)LPUARTRST 0 (USARTRST)USARTRST 0 (SPI3RST)SPI3RST 0 (I2C1RST)I2C1RST 0 (I2C2RST)I2C2RST

Description

APB1RSTR register

Fields

SPI1RST

SPI1 reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset.
ADCRST

ADC reset for Aux-ADC IP Set and reset by software. 0: IP is not under reset. 1: IP is under reset.
LPUARTRST

LPUART reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset.
USARTRST

USART reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset.
SPI3RST

SPI3 reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset.
I2C1RST

I2C1 reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset.
I2C2RST

I2C2 reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32