stm32 /stm32wl3 /STM32WL33 /RCC /APB1SMENR

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Interpret as APB1SMENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI1SMEN)SPI1SMEN 0 (ADCDIGSMEN)ADCDIGSMEN 0 (LPUARTSMEN)LPUARTSMEN 0 (USARTSMEN)USARTSMEN 0 (SPI3SMEN)SPI3SMEN 0 (I2C1SMEN)I2C1SMEN 0 (I2C2SMEN)I2C2SMEN

Description

APB1SMENR register

Fields

SPI1SMEN

SPI1 bus clock enable during Sleep mode bit This bit is set and reset by software.

  • 0: SPI1 bus clock disabled in Sleep mode
  • 1: SPI1 bus clock enabled in Sleep mode (if enabled in SPI1EN)
ADCDIGSMEN

ADCDIG bus clock enable during Sleep mode bit This bit is set and reset by software.

  • 0: ADCDIG bus clock disabled in Sleep mode
  • 1: ADCDIG bus clock enabled in Sleep mode (if enabled by ADCDIGEN)
LPUARTSMEN

LPUART bus clock enable during Sleep mode bit This bit is set and reset by software.

  • 0: LPUART bus clock disabled in Sleep mode
  • 1: LPUART bus clock enabled in Sleep mode (if enabled in LPUARTEN)
USARTSMEN

USART bus clock enable during Sleep mode bit This bit is set and reset by software.

  • 0: USART bus clock disabled in Sleep mode
  • 1: USART bus clock enabled in Sleep mode (if enabled in USARTEN)
SPI3SMEN

SPI3 bus clock enable during Sleep mode bit This bit is set and reset by software.

  • 0: SPI3 bus clock disabled in Sleep mode
  • 1: SPI3 bus clock enabled in Sleep mode (if enabled in SPI3EN)
I2C1SMEN

I2C1 clock enable during Sleep mode bit This bit is set and reset by software.

  • 0: I2C1 clock disabled in Sleep mode
  • 1: I2C1 clock enabled in Sleep mode (if enabled in I2C1EN)
I2C2SMEN

I2C2 clock enable during Sleep mode bit This bit is set and reset by software.

  • 0: I2C2 clock disabled in Sleep mode
  • 1: I2C2 clock enabled in Sleep mode (if enabled in I2C2EN)

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