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stm32 /stm32wl3 /STM32WL33 /RCC /APB2ENR

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Interpret as APB2ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MRSUBGEN)MRSUBGEN 0 (LPAWUREN)LPAWUREN

Description

APB2ENR register

Fields

MRSUBGEN

MRSUBG clock enable. Note: when this bit is ‘1’, it must prevent clk_sys different from 16, 32, 64. If the configured clock is lower than 16MHz (1, 2, 4 or 8 MHz) or equal to 24MHz, clk_sys must be 16MHz 0: clock disable 1: clock enable
LPAWUREN

Bubble clock enable Set and enable by software. 0: clock disable 1: clock enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32