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stm32 /stm32wl3 /STM32WL33 /RCC /CIER

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Interpret as CIER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSIRDYIE)LSIRDYIE 0 (LSERDYIE)LSERDYIE 0 (HSIRDYIE)HSIRDYIE 0 (HSERDYIE)HSERDYIE 0 (HSIPLLRDYIE)HSIPLLRDYIE 0 (HSIPLLUNLOCKDETIE)HSIPLLUNLOCKDETIE 0 (RTCRSTIE)RTCRSTIE 0 (WDGRSTIE)WDGRSTIE 0 (LPURSTIE)LPURSTIE 0 (LCDRSTIE)LCDRSTIE 0 (LCSCRSTIE)LCSCRSTIE

Description

CIER register

Fields

LSIRDYIE

LSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled
LSERDYIE

LSE Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled
HSIRDYIE

HSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled
HSERDYIE

HSE Ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled
HSIPLLRDYIE

HSI PLL Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE. 0: HSI PLL ready interrupt disabled 1: HSI PLL ready interrupt enabled
HSIPLLUNLOCKDETIE

HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock. 0: HSI PLL unlock detection interrupt disabled 1: HSI PLL unlock detection interrupt enabled
RTCRSTIE

RTCRSTIE: RTC reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the RTC reset end. 0: HSI PLL unlock detection interrupt disabled 1: HSI PLL unlock detection interrupt enabled
WDGRSTIE

WDGRSTIE: Watchdog reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the watchdog reset end. 0: interrupt disabled 1: interrupt enabled
LPURSTIE

LPURSTIE: LPUART reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the LPUART reset end. 0: interrupt disabled 1: interrupt enabled
LCDRSTIE

LCDRSTIE: LCD reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the LCD reset end. 0: interrupt disabled 1: interrupt enabled
LCSCRSTIE

LCSCRSTIE: LCSC reset release interrupt enable. 0: LCSC reset release interrupt is disabled. 1: LCSC reset release interrupt is enabled.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32