stm32 /stm32wl3 /STM32WL33 /RCC /CIFR

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Interpret as CIFR

Description

CIFR register

Fields

LSIRDYIF	LSI Ready Interrupt flag Set by hardware when LSI clock becomes stable. 0: No clock ready interrupt caused by the internal RC 32 KHz oscillator 1: Clock ready interrupt caused by the internal RC 32 kHz oscillator
LSERDYIF	LSE Ready Interrupt Flag. Set by hardware when LSE clock becomes stable. 0: No clock ready interrupt caused by the LSE oscillator 1: Clock ready interrupt caused by the LSE oscillator
HSIRDYIF	HSI Ready Interrupt Flag. Set by hardware when HSI becomes stable. 0: No clock ready interrupt caused by the HSI oscillator 1: Clock ready interrupt caused by the HSI oscillator
HSERDYIF	HSE Ready Interrupt Flag. Set by hardware when HSE becomes stable. 0: No clock ready interrupt caused by the HSE oscillator 1: Clock ready interrupt caused by the HSE oscillator
HSIPLLRDYIF	HSI PLL Ready Interrupt Flag. Set by hardware when HSI PLL 64MHz becomes stable. 0: No clock ready interrupt caused by the HSI PLL64 MHz oscillator 1: Clock ready interrupt caused by the HSI PLL64 MHz oscillator
HSIPLLUNLOCKDETIF	HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag.
RTCRSTIF	RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock
WDGRSTIF	WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock
LPURSTIF	LPUART reset end Interrupt Flag. Raised when reset is released on 32kHz clock
LCDRSTIF	LCD reset end Interrupt Flag. Raised when reset is released on 32kHz clock
LCSCRSTIF	LCSC reset end Interrupt Flag. Raised when reset is released on 32kHz clock

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