stm32 /stm32wl3 /STM32WL33 /RCC /DBGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DBGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBGHSIOFF)DBGHSIOFF 0 (DBGBYPHSI)DBGBYPHSI 0 (DBGXOEXT)DBGXOEXT 0 (FORCEXO48MREADY)FORCEXO48MREADY

Description

DBGR register

Fields

DBGHSIOFF

used for debug or test 0: No effect (default) 1: HSI forced off.

DBGBYPHSI

used for debug mode with HSI bypassed by HSE 0: No effect (default) 1: HSI bypassed HSE.

DBGXOEXT

used for debug mode with HSE bypassed by FXTAL_IN clock and ZIV12 output used. 0: No effect (default) 1: HSE bypassed by FXTAL_IN clock and ZIV12 output used.

FORCEXO48MREADY

FORCEXO48MREADY Force XO48M Ready input signal This bit is for debug and force the XO48M ready input, in order to bypass XO48M comparators. 0: No effect (default) 1: Force XOREADY=1

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