KRM[4:0] :SMPS clock dividing Ratio (CLK_SPMS_KRM frequency= CLK_ROOT frequency
(depending on RCC_CFGR.HSESEL) divided by KRM when KRMEN=1)
Reset source only for this field: PORESETn
- 0x00 to 0x08: SMPS clock frequency equals CLK_ROOT/8 (8.00 MHz / 6.00 MHz)
- 0x09: SMPS clock frequency equals CLK_ROOT/9 (7.11 MHz / 5.33 MHz)
- 0x0A: SMPS clock frequency equals CLK_ROOT/10 (6.40 MHz / 4.80 MHz)
- 0x0B: SMPS clock frequency equals CLK_ROOT/11 (5.82 MHz / 4.36 MHz)
- 0x0C: SMPS clock frequency equals CLK_ROOT/12 (5.33 MHz / 4.00 MHz)
- 0x0D: SMPS clock frequency equals CLK_ROOT/13 (4.92 MHz / 3.69 MHz)
- 0x0E: SMPS clock frequency equals CLK_ROOT/14 (4.57 MHz / 3.43 MHz)
- 0x0F: SMPS clock frequency equals CLK_ROOT/15 (4.27 MHz / 3.20 MHz)
- 0x10: SMPS clock frequency equals CLK_ROOT/16 (4.00 MHz / 3.00 MHz)
- 0x1x: Reserved
Note: SMPS clock frequency must be selected in a range [4-8] MHz (depending on
RCC_KRMR.KRM and RCC_CFGR.HSESEL).