stm32 /stm32wl3 /STM32WL33 /SPI3 /SPI2S_I2SCFGR

Channel length (number of bits per audio channel)

• 0: 16-bit wide
• 1: 32-bit wide The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in.

Data length to be transferred

• 00: 16-bit data length
• 01: 24-bit data length
• 10: 32-bit data length
• 11: Not allowed

Steady state clock polarity

• 0: I2S clock steady state is low level
• 1: I2S clock steady state is high level

I2S standard selection

• 00: I2S Philips standard.
• 01: MSB justified standard (left justified)
• 10: LSB justified standard (right justified)
• 11: PCM standard

PCM frame synchronization

• 0: Short frame synchronization
• 1: Long frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode.

I2S configuration mode

• 00: Slave - transmit
• 01: Slave - receive
• 10: Master - transmit
• 11: Master - receive

I2S enable

• 0: I2S peripheral is disabled
• 1: I2S peripheral is enabled Note: This bit is not used in SPI mode.

I2S mode selection

• 0: SPI mode is selected
• 1: I2S mode is selected Note: This bit should be configured when the SPI is disabled.

Asynchronous start enable. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards.

0 (B_0x0): The Asynchronous start is disabled. When the I2S is enabled in slave mode, the I2S slave starts the transfer when the I2S clock is received and an appropriate transition (depending on the protocol selected) is detected on the WS signal.

1 (B_0x1): The Asynchronous start is enabled. When the I2S is enabled in slave mode, the I2S slave starts immediately the transfer when the I2S clock is received from the master without checking the expected transition of WS signal.