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stm32 /stm32wl3 /STM32WL33 /SPI3 /SPI2S_I2SPR

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Interpret as SPI2S_I2SPR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2SDIV0 (ODD)ODD 0 (MCKOE)MCKOE

Description

SPI2S_I2SPR register

Fields

I2SDIV

I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
ODD

Odd factor for the prescaler

  • 0: Real divider value is = I2SDIV *2
  • 1: Real divider value is = (I2SDIV * 2)+1
MCKOE

Master clock output enable

  • 0: Master clock output is disabled
  • 1: Master clock output is enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32