stm32 /stm32wl3 /STM32WL33 /SPI3 /SPI_SSPCR1

Clock phase

• 0: The first clock transition is the first data capture edge
• 1: The second clock transition is the first data capture edge

Clock polarity

• 0: CK to 0 when idle
• 1: CK to 1 when idle

Master selection

• 0: Slave configuration
• 1: Master configuration

Baud rate control

• 000: fPCLK/2
• 001: fPCLK/4
• 010: fPCLK/8
• 011: fPCLK/16
• 100: fPCLK/32
• 101: fPCLK/64
• 110: fPCLK/128
• 111: fPCLK/256

SPI enable

• 0: Peripheral disabled
• 1: Peripheral enabled

Frame format

• 0: data is transmitted / received with the MSB first
• 1: data is transmitted / received with the LSB first

Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored.

Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.

• 0: Software slave management disabled
• 1: Software slave management enabled

Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted.

• 0: Full duplex (Transmit and receive)
• 1: Output disabled (Receive-only mode)

CRC length This bit is set and cleared by software to select the CRC length.

• 0: 8-bit CRC length
• 1: 16-bit CRC length

Transmit CRC next

• 0: Next transmit value is from Tx buffer
• 1: Next transmit value is from Tx CRC register

Hardware CRC calculation enable

• 0: CRC calculation disabled
• 1: CRC calculation Enabled

Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode

• 0: Output disabled (receive-only mode)
• 1: Output enabled (transmit-only mode)

Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active.

• 0: 2-line unidirectional data mode selected
• 1: 1-line bidirectional data mode selected