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stm32 /stm32wl3 /STM32WL33 /SYSTEM_CTRL /INTAI_DTR

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Interpret as INTAI_DTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_DT)TX_DT 0 (RX_DT)RX_DT 0 (COMP_DT)COMP_DT 0 (RFIP_BUSY_STATUS_DT)RFIP_BUSY_STATUS_DT

Description

INTAI_DTR register

Fields

TX_DT

TX_DT: detection type on TX_SEQUENCE signal: 0: detection on edge (default). 1: detection on level
RX_DT

RX_DT: detection type on RX_SEQUENCE signal: 0: detection on edge (default). 1: detection on level
COMP_DT

COMP_DT: detection type on COMP_OUT (after COMP_POL selection) signal: 0: detection on edge (default). 1: detection on level
RFIP_BUSY_STATUS_DT

RFIP_BUSY_STATUS_DT: detection type on RFIP_BUSY_STATUS signal: 0: detection on edge (default). 1: detection on level

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32