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stm32 /stm32wl3 /STM32WL33 /SYSTEM_CTRL /SYSCFG_SR1

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Interpret as SYSCFG_SR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RFIP_BUSY_STATUS)RFIP_BUSY_STATUS

Description

SYSCFG_SR1 register

Fields

RFIP_BUSY_STATUS

RFIP_BUSY_STATUS: MR_SUBG BUSY status: Software should check that MR_SUBG IP is not busy (or relay on the related interrupt) before to initiate any system clock frequency switch to operate the switching in a safe way. 0: MR_SUBG is not busy. 1: MR_SUBG is busy

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32