SMCR register
| SMS_2_0 | SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. |
| TS_2_0 | TS[4:0]: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 00000: Internal Trigger 0 (ITR0) 00001: Internal Trigger 1 (ITR1) 00010: Internal Trigger 2 (ITR2) 00011: Internal Trigger 3 (ITR3) 00100: TI1 Edge Detector (TI1F_ED) 00101: Filtered Timer Input 1 (TI1FP1) Other codes: Reserved Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. See Table 79 in IUM: TIM16 register map and reset values on page 469 for more details on ITRx meaning for each Timer. |
| MSM | MSM: Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. |
| SMS_3 | SMS[3:0]: Slave mode selection. See SMS_LSB description |
| TS_4_3 | TS[4:0]: Trigger selection. See TS_LSB description |